I have found the solution. The required directive is .balgin.
.balign[wl] abs-expr, abs-expr, abs-expr
Pad the location counter (in the current subsection) to a particular
storage boundary. The first expression (which must be absolute) is the
alignment request in bytes. For example `.balign 8' advances the
location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed.
The second expression (also absolute) gives the fill value to be
stored in the padding bytes. It (and the comma) may be omitted. If it
is omitted, the padding bytes are normally zero. However, on some
systems, if the section is marked as containing code and the fill
value is omitted, the space is filled with no-op instructions.
The third expression is also absolute, and is also optional. If it is
present, it is the maximum number of bytes that should be skipped by
this alignment directive. If doing the alignment would require
skipping more bytes than the specified maximum, then the alignment is
not done at all. You can omit the fill value (the second argument)
entirely by simply using two commas after the required alignment; this
can be useful if you want the alignment to be filled with no-op
instructions when appropriate.
The .balignw and .balignl directives are variants of the .balign
directive. The .balignw directive treats the fill pattern as a two
byte word value. The .balignl directives treats the fill pattern as a
four byte longword value. For example, .balignw 4,0x368d will align to
a multiple of 4. If it skips two bytes, they will be filled in with
the value 0x368d (the exact placement of the bytes depends upon the
endianness of the processor). If it skips 1 or 3 bytes, the fill value
is undefined.
Quote from the GAS manual
The following works as excepted:
_vec_tbl_s:
_vec_tbl_cur_sp0:
_vec_tbl_cur_sp0_syn:
mov x0, #0x0
bl _vec_handler_syn
eret
.balign 128
_vec_tbl_cur_sp0_irq:
mov x0, #0x0
bl _vec_handler_irq
eret
.balign 128
_vec_tbl_cur_sp0_fiq:
mov x0, #0x0
bl _vec_handler_fiq
eret
.balign 128
_vec_tbl_cur_sp0_err:
mov x0, #0x0
bl _vec_handler_err
eret
.balign 128
The disassembled binary:
$ aarch64-none-elf-objdump -d vector.o
vector.o: file format elf64-littleaarch64
Disassembly of section .text:
0000000000000000 <_vec_tbl_cur_sp0>:
0: d2800000 mov x0, #0x0 // #0
4: 940001ff bl 800 <_vec_handler_syn>
8: d69f03e0 eret
c: d503201f nop
10: d503201f nop
14: d503201f nop
18: d503201f nop
1c: d503201f nop
20: d503201f nop
24: d503201f nop
28: d503201f nop
2c: d503201f nop
30: d503201f nop
34: d503201f nop
38: d503201f nop
3c: d503201f nop
40: d503201f nop
44: d503201f nop
48: d503201f nop
4c: d503201f nop
50: d503201f nop
54: d503201f nop
58: d503201f nop
5c: d503201f nop
60: d503201f nop
64: d503201f nop
68: d503201f nop
6c: d503201f nop
70: d503201f nop
74: d503201f nop
78: d503201f nop
7c: d503201f nop
0000000000000080 <_vec_tbl_cur_sp0_irq>:
80: d2800000 mov x0, #0x0 // #0
84: 940001e1 bl 808 <_vec_handler_irq>
88: d69f03e0 eret
8c: d503201f nop
90: d503201f nop
94: d503201f nop
98: d503201f nop
9c: d503201f nop
a0: d503201f nop
a4: d503201f nop
a8: d503201f nop
ac: d503201f nop
b0: d503201f nop
b4: d503201f nop
b8: d503201f nop
bc: d503201f nop
c0: d503201f nop
c4: d503201f nop
c8: d503201f nop
cc: d503201f nop
d0: d503201f nop
d4: d503201f nop
d8: d503201f nop
dc: d503201f nop
e0: d503201f nop
e4: d503201f nop
e8: d503201f nop
ec: d503201f nop
f0: d503201f nop
f4: d503201f nop
f8: d503201f nop
fc: d503201f nop
0000000000000100 <_vec_tbl_cur_sp0_fiq>:
100: d2800000 mov x0, #0x0 // #0
104: 940001c3 bl 810 <_vec_handler_fiq>
108: d69f03e0 eret
10c: d503201f nop
110: d503201f nop
114: d503201f nop
118: d503201f nop
11c: d503201f nop
120: d503201f nop
124: d503201f nop
128: d503201f nop
12c: d503201f nop
130: d503201f nop
134: d503201f nop
138: d503201f nop
13c: d503201f nop
140: d503201f nop
144: d503201f nop
148: d503201f nop
14c: d503201f nop
150: d503201f nop
154: d503201f nop
158: d503201f nop
15c: d503201f nop
160: d503201f nop
164: d503201f nop
168: d503201f nop
16c: d503201f nop
170: d503201f nop
174: d503201f nop
178: d503201f nop
17c: d503201f nop
0000000000000180 <_vec_tbl_cur_sp0_err>:
180: d2800000 mov x0, #0x0 // #0
184: 940001a5 bl 818 <_vec_handler_err>
188: d69f03e0 eret
18c: d503201f nop
190: d503201f nop
194: d503201f nop
198: d503201f nop
19c: d503201f nop
1a0: d503201f nop
1a4: d503201f nop
1a8: d503201f nop
1ac: d503201f nop
1b0: d503201f nop
1b4: d503201f nop
1b8: d503201f nop
1bc: d503201f nop
1c0: d503201f nop
1c4: d503201f nop
1c8: d503201f nop
1cc: d503201f nop
1d0: d503201f nop
1d4: d503201f nop
1d8: d503201f nop
1dc: d503201f nop
1e0: d503201f nop
1e4: d503201f nop
1e8: d503201f nop
1ec: d503201f nop
1f0: d503201f nop
1f4: d503201f nop
1f8: d503201f nop
1fc: d503201f nop
Sorry, asked too quickly.
