What does the notation "::*" mean in SystemVerilog?

1
votes

This example was taken from a uvm_users_guide_1.1, page 27:

`timescale 1ns/1ps

 package a_pkg;
  class a;
    function void f(inout time t);
     t += 10ns;
    endfunction
  endclass
 endpackage


 program p;
   import a_pkg::*;
   ...
 endprogram

Is the :: the same as . ? And what does the * stand for?

1
system-verilog

1 Answers

1
votes

Refer to IEEE Std 1800-2017, section 26.3 Referencing data in packages. The ::* syntax is a wildcard import, defined as:

A wildcard import allows all identifiers declared within a package to be imported provided the identifier is not otherwise defined in the importing scope

:: is the package scope resolution operator. * allows all identifiers to be imported, as opposed to explicitly name identifiers to be imported.

In your example, it allows access to the a class inside the p program.