2
votes

Just noticed you can do something like:

class MyBundle1 extends Bundle {
  val a = Bool()
  val x = UInt(2.W)
  val y = Bool()
}

class MyBundle2 extends Bundle {
  val x = Bool()
  val y = Bool()
}

class Foo extends Module {
  val io = IO(new Bundle {
    val in = Input(new MyBundle1)
    val out = Output(new MyBundle2)
  })

  io.out := io.in
}

not get an error and actually get the correct or, at least, expected verilog. One would think that Chisel was type-safe wrt to Bundles in this sort of bulk connection. Is this intentional? If so, is there any particular reasons for it?

1

1 Answers

3
votes

The semantics of := on Bundle allow the RHS to have fields that are not present on the LHS, but not vice-versa. The high-level description of x := y is "drive all fields of x with corresponding fields of y."

The bi-directional <> operator is stricter.

I can't speak precisely to the reasoning, but connection operators are often a matter of taste with respect to "do what I mean." The idea of including alternate forms of connection operators for future releases is an ongoing discussion, with the threat of "operator glut" being weighed against the ability of users to specify exactly what they'd like to do.