Is there any way to use chisel to generate blackbox from verilog text content? (define val based on text content in scala)

Question

I'm working with a team that use verilog as well. I feel it is way faster to use chisel power to manage the interconnections between modules than bare verilog. I can see from the chisel tutorial that blackbox wrappers are written manually.The io signals are defined by hand.

Is it possible to extract the io info from verilog and define chisel blackbox io automatically? (aka, generate a blackbox from verilog instead of defining a blackbox class by some human being by reading the verilog. )

for example:

val bbox = blackbox("someModule.v")

and then, the bbox will be an functioning blackbox with all the ios and name defined.

Since the io signal is vals in scala, I wonder if there is a meta way towards this goal.

Jack Koenig Jack Koenig · Accepted Answer · 2020-03-31T17:10:53

Yes there is! Check out HasBlackBoxInline:

https://www.chisel-lang.org/chisel3/blackboxes.html#blackboxes-with-in-line-verilog

class BlackBoxRealAdd extends BlackBox with HasBlackBoxInline {
  val io = IO(new Bundle() {
    val in1 = Input(UInt(64.W))
    val in2 = Input(UInt(64.W))
    val out = Output(UInt(64.W))
  })
  setInline("BlackBoxRealAdd.v",
    s"""
      |module BlackBoxRealAdd(
      |    input  [15:0] in1,
      |    input  [15:0] in2,
      |    output [15:0] out
      |);
      |always @* begin
      |  out <= $realtobits($bitstoreal(in1) + $bitstoreal(in2));
      |end
      |endmodule
    """.stripMargin)
}

By default this BlackBox will be emitted to the output directory with its given name.

Is there any way to use chisel to generate blackbox from verilog text content? (define val based on text content in scala)

1 Answers