Are system registers banked per processor on ARMv8-A?

Question

Are system registers banked per processor on ARMv8? I thought they weren't, which is why they were called system registers, but I'm now confused.

My understanding is that on multi-core ARMv8-A implementations different cores can be executing at different exception levels at any time. So what happens when you have different threads executing on different physical CPUs, each of which changing system registers according to their needs?

For example, I was reading about virtualization for a school project and saw some open source code, and I see system registers being saved and restored as part of "vCPU" thread contexts. If one core is executing a vCPU thread but another isn't, wouldn't they have conflicting system register states?

Answer 1

I would not use the work 'banked' in this context - a register in an arm core would be 'banked' in the case there would be different copies of the same register accessible depending on the core state.

For example, in an Armv8-A core, TTBR0_EL1 is accessible from EL1, EL2, and EL3. TTBR0_EL2 is accessible from EL2 and EL3 - This is a way to model the fact that the conceptual system register TTBR0 is banked.

But all the system registers as defined in the Registers Armv8, for Armv8-A architecture profile Documentation are present in a Armv8-a core.

That is, in a multi-core system, each core does have its own set of the system registers as defined in the documentation referenced above: the "System Registers" could be more specifically called "Core System Registers" in this context.

If you think about it, the MSR and MRS instructions being executed in a specific core do affect the general purpose and system registers of the same core:

MRS  x0, TTBR0_EL1          // Move TTBR0_EL1 into x0
MSR  TTBR0_EL1, x0          // Move x0 into TTBR0_EL1