For a given project I encountered with floating point multiplication in verilog. So I used from IP cores of Xilinx in ISE 14.7 with following configurations for floating point IP core GUI:
- Multiply
- Single (Exponent width : 8 bit, fraction width : 24)
- No usage (in family optimization)
- maximum latency (which is here 8 clock cycles)
so when I give the following inputs in ieee 754 format
A = 0_0111111_000000000000000000000000 (which is one)
B = 0_0111111_000000000000000000000000
the result after 8 clock cycles is :
0_0111110_100000000000000000000000
my question is why the result is not one in ieee 754 format? who is wrong?
A
is1
isn't correct. It actually is0.5
. And the result decodes as0.25
which is the correct answer. See below for details. – alias