0
votes

Say I have a set of Makefile modules:

# foo.mk

rule1: prereq1
    recipe1

and

# bar.mk

rule2: prereq2
    recipe2

and a primary Makefile:

# Makefile

include foo.mk
include bar.mk

Should .PHONY: be included in each individual .mk file for the phony targets just in that file, or should there be some acculmulated list that is included only in the primary Makefile?

# foo.mk
TARGETS += rule1
...
# bar.mk
TARGETS += rule2
...
# Makefile
.PHONY: $(TARGETS)

I didn't find anything relevant in the GNU Make docs or similar questions.

1
I don't know what you mean by "should". Either way works fine so do whichever one you prefer.MadScientist
"Should" ... as in, is there a best practice or documented & defined way to do something. I don't want to put .PHONY in each file declaring the relevant targets if it's overridden the next time it's encountered.Kurt E. Clothier
.PHONY is never overridden. Like any other target, each new .PHONY definition adds more prerequisites to the existing list. No, there is no best practice that I'm aware of. Both work identically (except one has a variable defined, which might be useful for other things besides .PHONY, and one doesn't). For the same reason there's no need for a "documented & defined" method. Whichever one you like better, you should use.MadScientist
That's what I was looking for. thank you!Kurt E. Clothier

1 Answers

1
votes

The statement

.PHONY: rule1

tells Make that it should not consider "rule1" the name of a file to be built. Suppose you put it in the Makefile. What happens when you run another makefile, either foo.mk or a makefile that includes it?

When you run the rule1 rule, do you want Make to treat it as a PHONY target? If your answer isn't "that depends on which makefile I'm using", then you should have the statement in the makefile that defines the rule.