always @ (posedge clk ) not triggering as expected

0
votes

always block is not triggering continuously

always@(posedge clk) begin
    for (int i=1;i<=32;i=i+1) begin
       clk_a=i;
       #0.3215
    end
    for (int j=31;j>=0;j=j-1) begin
       clk_a=j;
       #0.3215
    end
    clk_a=0;
    end

In 5th clk always block is not triggered ||y for 7th and 9th clocks and this behavior is happening randomly through the simulation. enter image description here

1
verilogsystem-verilog
1/ What is the frequency of your clk. 2/ What is your `timescale set to? - Oldfart

1 Answers

1
votes

I assume your time precision is small enough so that 0.3215 is not getting rounded to 0.322. Also I assume you have typos in your two for loops.

First loop: i<=32 should be i<32
Second loop: j=j+1 should be j--.

The only other possible explanation is you have a race condition with the end of the second loop and the next @(posedge clk). You should try:

initial @(posedge clk) 
  forever begin
    for (int i=0;i<32;i++) begin
       clk_a=i;
       #0.3215
    end
    for (int j=31;j>=0;j--) begin
       clk_a=j;
       #0.3215
    end
    clk_a=0;
  end