How can I force vivado to use dsp blocks for all arithmetic operations

Question

I am trying to implement a riscv core on a ZYNQ fpga. I am doing some optimization ways to increase its performance.

How can I force xilinx vivado to use DSPs for any arithmetic operation on my design?

Sorry for the counter question but: why do yo think you need to force this? Did you write some code and the DSP did not appear? My experience is that Vivado always uses DSPs for big multiply-add operations unless it has runs out of them. You can always manually instance them but that is difficult and error prone. — Oldfart

fgagnaire fgagnaire · Accepted Answer · 2019-08-26T03:11:44

I think that normally Vivado will use DSP evry time it can.

you may want to try to add the attribute "use_dsp" every time you would like to see a DSP, to force vivado to infer it. doc: (search for USE_DSP page 66) https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

as a side note. In the doc, page 88, there is a good explanation about what Vivado is doing with multiplier.

I do not think that there is way to ask vivado to be "more aggressive" in term of inferring the multiplier. (look at page 44 to see the options)