Conditional use of libraries when simulating VHDL design with ModelSim in Pre-Synthesis / Post-Synthesis

Question

In my VHDL design there is a 16-bits std_logic_vector. The bit in position 15 is currently not used and the synthesizer (SynplifyPro) throws a warning saying that bit is not used and will be pruned:

@W:CL190 : DATAGEN.vhd(93) | Optimizing register bit MYREG(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : DATAGEN.vhd(93) | Pruning register bit 15 of MYREG(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.

As suggested by the synthesizer, I have added the required attribute and I was able to get rid of these warnings. To add these attributes, I had to include the Synplify library:

library synplify;

at the top of the file, and then define the attribute as follows:

ATTRIBUTE SYN_PRESERVE : BOOLEAN;
ATTRIBUTE SYN_PRESERVE OF MYREG : SIGNAL IS TRUE;

If I try to run ModelSim on Post-Synthesis everything is fine. However, when I try to run ModelSim on Pre-synthesis, it gives me the error:

** Error: .../DATAGEN.vhd(20): (vcom-1598) Library "synplify" not found.

I believe that the problem is because Pre-Synthesis simulation is not supposed to use this library. In fact, if I remove this everything works. The reason for which I would like to keep using the Pre-Synthesis simulation is because it is much faster than Post-Synthesis. However, this issue forces me to keep commenting out this lib for Pre-synthesis and putting it back for Post-synthesis?

Is it possible to use something like conditional include?

Note: I prefer to keep the unused bits, therefore adding the attribute for avoid pruning works fine for me.

Library synplify; simply shouldn't be needed. Just remove it. — Tricky
I agree with Tricky that the library shouldn't be needed, but it should be possible to leave it in the file. Did you add it as extra external library in your vsim command? — DonFusili
@DonFusili: I'll try to do include synplify on the vsim command. Thank you. — Alexis Nicole
Show any use clauses or selected names with the library logical name synplify. Without any of those a library clause just makes the library logical name visible. The attribute declaration and attribute specification don't depend on the library clause. Preserving a flip flop whose output isn't used doesn't seems useful either. — user1155120

lasplund lasplund · Accepted Answer · 2019-07-24T08:00:20

Is it possible to use something like conditional include?

The upcoming VHDL-2019 standard supports conditional compilation and some simulators, for example RivieraPro, have started to support that. With such support you can do things like

`if INCLUDE_SYNPLIFY = "true" then
  library synplify;
`end if

I don't think ModelSim has that yet but what you can do is to just define a synplify library with vlib and include that when calling vsim. If you are using VUnit you can simply add the following to your run script

prj.add_library("synplify")

Conditional use of libraries when simulating VHDL design with ModelSim in Pre-Synthesis / Post-Synthesis

1 Answers