register initial values at testbench

Question

want to send an initial value to reg div_num_tb (it's a 8 bit register) and i get this error:

Error (10137): Verilog HDL Procedural Assignment error at top_tb.v(23): object "div_num_tb" on left-hand side of assignment must have a variable data type

other single bit registers doesn't do issues

module top_tb();
  reg clock_tb, reset_tb, enable_tb; 
  reg [7:0]Div_num_tb;
  wire Out_signal_tb; 
  wire [7:0]count_tb;`

Top U0(
  .clock (clock_tb),
  .reset (reset_tb),
  .enable (enable_tb),
  .Div_num (div_num_tb),
  .Div_num (Div_num_tb),
  .Out_signal (Out_signal_tb),
  .count (count_tb)
);

initial
begin   
  clock_tb = 0;
  reset_tb = 1;
  enable_tb = 0;
  div_num_tb = 8'b00000000;
end
endmodule

Error (10137): Verilog HDL Procedural Assignment error at top_tb.v(23): object "div_num_tb" on left-hand side of assignment must have a variable data type

Possible duplicate of Verilog Error: Object on left-hand side of assignment must have a variable data type — Qiu
@Qui - this is not a dupe. In the question you reference, the assignment is to a module port that defaults to a wire; in this question, the assignment is to an undeclared object, which unfortunately also defaults to a wire. — EML
Add a "`default_netype none" to your description to avoid your typos turning into wires. — EML

user11731474 user11731474 · Accepted Answer · 2019-07-02T22:22:38

Div_num_tb has been defined as a reg.

reg [7:0]Div_num_tb;

but not div_num_tb, which as a result, is being inferred as a wire. Verilog is case-sensitive.

register initial values at testbench

1 Answers