Suppose we have an interface like this:
interface Memory_i(input Clock);
Data_t InData;
Data_t OutData;
Address_t Address;
// To memory controller
modport Master
(
input Clock,
output InData,
input OutData,
output Address
);
// To memory
modport Slave
(
input Clock,
input InData,
output OutData,
input Address,
);
endinterface
Is there any significant difference between Clock (interface port) and, let us say, InData (interface signal)? I know that these entities are connected differently when an interface is instantiated. But is there something else? I also noticed that interface ports are frequently used for the clock signal. Is there a reason for that?
UPDATE
I simplified my interface and made two examples where I am trying to use clock in two different ways. I got two slightly different RTL circuits, but I cannot not see any fundamental difference between them.
Clock as a port:
interface CdcSignal_i(input clock);
logic data;
// To memory controller
modport Master
(
input clock,
output data
);
// To memory
modport Slave
(
input clock,
input data
);
endinterface
module Cdc(
CdcSignal_i.Slave slave,
CdcSignal_i.Master master
);
logic registerS;
logic registerM;
always_ff @(posedge slave.clock) begin
registerS <= slave.data;
end
always_ff @(posedge master.clock) begin
registerM <= registerS;
master.data <= registerM;
end
endmodule
module InterfaceTest(
input logic clock0,
input logic clock1,
input logic data0,
output data1);
CdcSignal_i signal0(clock0);
assign signal0.data = data0;
CdcSignal_i signal1(clock1);
assign data1 = signal1.data;
Cdc cdc(signal0, signal1);
endmodule
Clock as a signal:
interface CdcSignal_i();
logic data;
logic clock;
// To memory controller
modport Master
(
input clock,
output data
);
// To memory
modport Slave
(
input clock,
input data
);
endinterface
module Cdc(
CdcSignal_i.Slave slave,
CdcSignal_i.Master master
);
logic registerS;
logic registerM;
always_ff @(posedge slave.clock) begin
registerS <= slave.data;
end
always_ff @(posedge master.clock) begin
registerM <= registerS;
master.data <= registerM;
end
endmodule
module InterfaceTest(
input logic clock0,
input logic clock1,
input logic data0,
output data1);
CdcSignal_i signal0();
assign signal0.clock = clock0;
assign signal0.data = data0;
CdcSignal_i signal1();
assign signal1.clock = clock1;
assign data1 = signal1.data;
Cdc cdc(signal0, signal1);
endmodule
