ALU in Verilog: “Unable to bind wire/reg/memory”

3
votes

I am trying to make a simple 32 bit ALU with an overflow flag, and then output the inputs and results of the ALU to the screen, but I encountered some problems with connecting the elements for the test bench. I got this error:

test_32bALU.v:15: error: Wrong number of ports. Expecting 4, got 5. test_32bALU.v:33: error: Unable to bind wire/reg/memory test_unit.overflow' inalu_test'

2 error(s) during elaboration.

I am just starting with Verilog and I have a basic idea of the syntax. I know I am not supposed to ask debugging questions, but this is my only hope. My professor or TA wouldn't respond to me requests for help. I would appreciate it if anyone here could help me point out my mistakes.

This is my 32bALU.v file:

module alu(
    input signed[31:0] a,b,
    input[3:0] opcode;
    output signed[31:0] c;
    output overflow;
    );

reg signed[31:0] result;
assign c = result;

reg tmp;

parameter
add = 4'b0000,
sub = 4'b0110,
sla = 4'b0001,
srai = 4'b0011;

always @(a,b,opcode)
begin

    case(opcode)
        add:
        begin
            c = a + b;
        end 

  endcase
end

always @(c)
begin

    if (c[32:31] == (2'b11 | 2'b10)) // Overflow
    begin
        tmp = 1'b1;
        assign overflow = tmp;
    end
    else begin
        tmp = 1'b0;
        assign overflow = tmp;
    end 
end

assign result = c[31:0];

endmodule

test_32bALU.v

`timescale 1ns/1ps

module alu_test;

// Inputs
reg[31:0] a,b;
reg[2:0] opcode;

// Outputs
wire[31:0] c;
//wire [1:0] zero;
wire [1:0] overflow;
//wire [1:0] neg;

alu test_unit(
    a,b, // Inputs
    opcode,
    c,
    overflow
);

parameter
add = 4'b0000,
sub = 4'b0110,
sla = 4'b0001,
srai = 4'b0011;

initial begin

$display("op: a      : b      : c      : reg_A  : reg_B  : reg_C");
$monitor(" %h:%h:%h:%h:%h:%h:%h",
opcode, a, b, c, test_unit.a, test_unit.b, test_unit.c);
$monitor("%h", test_unit.overflow);

//// add
#10 a=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#10 b=32'b0000_0000_0000_0000_0000_0000_0000_0001;
opcode= add;//3'b000

#10 $finish;

end
endmodule

I am confused as to why it says "wrong number of ports"? I assume it's the number of parameters in module alu and alu test_unit? They have the same number of parameters (a, b, c, opcode and overflow), so what exactly am I missing? How exactly do I get the value of overflow? It works fine before I added the overflow parameter, so I assume I'm doing it wrong?

For the second error, I read somewhere on here that it might be due to a missing declaration, but I have declared all of them... so I am not sure what's making it wrong.

2
verilogmodelsimalu

2 Answers

3
votes

I am not sure if this is the issue, but your module definition is not correct. It should be as follows:

module alu(
    input signed[31:0] a,b,
    input[3:0] opcode,
    output signed[31:0] c,
    output overflow
    );

Perhaps this may help with your issue.

2
votes

Commas separate inputs and outputs in the module declaration.

NEVER rely on the order of arguments to modules and ALWAYS try to use, for a module called A;

module A(output wire c, 
         input  wire a, 
         input  wire b);
...
endmodule // A

use an instance of it using;

A yourAname(.c(Bar), 
            .a(Foo1), 
            .b(Foo2));

so that if the definition and order of the I/O of the module changes, this instantiation will track those changes and/or give appropriate errors when simulated/synethesised.

You might find it useful to follow a few simple rules in your source code when naming;

inputs  are denoted by  i_yourinputname
outputs are denoted by  o_youroutputname
inout   are denoted by io_yourinputoutputname
wire    are denoted by  w_yourwirename
reg     are denoted by  r_yourregname

as this avoid confusion and is a good habit to get into as soon as possible when starting to learn verilog.