How were branch instructions implemented on 6502 microcprocessor?

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There are a lot of ways how to implement a branch instruction into the controller/sequencer hardware. I have done it myself before with my own method, but my question is: how was it done on the 6502 microprocessor and is there a universtal or at least a popular way of designing hardware for branch instructions?

(Additional information) The method I used was I added flags pins attached to opcode bus that when set high during specific branch instruction would load the value of specific flag into the decoder ROM, thus executing branch if flag was high/low and skipping branch if flag was low/high. For example, during BNE (Branch on Not Equal) intruction, on specific clock cycle the "Zero flag" pin would be activated. If the pin is low, then it doesen't change the opcode and the decoder normally goes to next memory location to execute next microinstruction set which in this case is ending BNE instruction without branching and then waiting for new instruction. However, if the "Zero flag" pin is high then it changes the opcode, thus making decoder skip to the new address (which is equal to opcode) where it will read a different set of microinstructions which will execute the branch instead of just ending/ignoring it.

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microcontrollerhardwareinstructionsdecoder6502
are you making a 6502 clone or making a processor in general. the 6502 isnt bad but is it really what you want to model yours from? There is no right answer obviously and it depends on the instruction set, for example an arm you have multiple program counters the fake one used in math with r15, the one actually prefetching at a minimum. If your instruction set doesnt have an exposed program counter then it depends on how you compute pc relative addressing, relative branches and possibly relative data accesses as to whether you can use a single pc for that and fetching. – old_timer
you look at a 6502 or other in that era and they would appear to have a single program counter that does the fetching and when you get to execution is pointing at the next instruction. if I remember my 6502 correctly. Remember these chips were drawn by hand on paper, every transistor. lean and mean – old_timer
as pointed out the visual6502 folks have learned an aweful lot from reverse engineering for whatever reason you are interested in the 6502 that is a good resource. note there are 6502 open cores out there you can download and examine as well... – old_timer
I wouldnt change the opcode I would have a state machine and state variables. unless there are enough free opcodes left in the chart to cover these states you want to change to. – old_timer
@old_timer I'm not trying to make an exact replica of 6502, I just want to build a processor that will work the same way. I'm doing all of that in a simulator (Logisim), not in real life. I haven't heared of opencores, will check out 6502 on their site once my registering there is complete. Haven't heared of state machines and variables either. I suppose I'll just make the branching hardware/software the best way I can think of. – Senijs

1 Answers

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First of all, the opcode does not change, ever.

Unless you have insider information about the 6502's "microcode" you can't possibly know the exact implementation. A datasheet only gives you the operation that is performed, but it rarely gives details as to how exactly this is accomplished. One can only guess.

One such guess:

  1. The corresponding Condition Code Register bit (normal or inverted depending on the instruction) masks the branch instruction operand to zero if the branch should not be taken.

  2. The (now possibly masked) 8-bit signed offset is added to the PC.