Problem with Verilog Dataflow testbench causing different errors on different sites

Question

This program is in Dataflow Verilog. What I'm trying to do is make an adder and subtractor dependent on a selector. I am currently getting some errors that are either "syntax error in continuous assignment" for line 10, (the assign {cout...},) or "Error launching EPWave: [Could not parse file: $timescale not found in the header.]. Could not load './dataflow_hw_1.vcd'".

I have looked all over the internet in search of how to solve this problem, but I keep attempting the recommended solutions to no avail. I don't know what's wrong when trying to testbench it.

Here is the code:

module dataflow_1 (a[7:0],b[7:0],out[7:0],cout);

  input a,b;
  output out,cout;
  //if a have odd number of 1s, output = a + b
  //else if even positions have even number of 1s in total, output = a-b

  assign selectorOdd = (a[1]^ a[3]^ a[5] ^ a[7]);
  assign selectorEven = (~selectorOdd & ~(a[0] ^ a[2] ^ a[4] ^ a[6])); 
  assign {cout,out[7:0]} = (selectorOdd & ({a[7:0] + b[7:0}) | (selectorEven & ({a[7:0] - b[7:0]}));


endmodule

Here is the testbench code:

// Code your testbench here
module dataflow_1();

  reg [7:0] a;
  reg [7:0] b;
  wire [7:0] out;


   dataflow_1  test(
     .a(a),
     .b(b),
     .out(out)
  );

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, out);

    a = 8'b01010101;
    b = 8'b00000001;
  #100;

  end



endmodule

well, you do have a syntactic error there. Check for use of [] and {} in this statement. — Serge
If you're talking about line 10 missing a closing bracket on b[7:0] I've already tried that — zebermeken
and what happened? btw, what is the meaning of braces {} there in the first place? — Serge
It didn't change anything, but you're right, they should be there. The point of the curly braces {} are to concatenate the bits — zebermeken
I notice both modules are called dataflow_1. Whichever is compiled second will overwrite whichever is compiled first. In the case of EDA Playground, the design is compiled before the testbench. — Matthew Taylor

thangpx1706 thangpx1706 · Accepted Answer · 2019-02-22T05:22:34

The problem is on this line:

assign {cout,out[7:0]} = (selectorOdd & ({a[7:0] + b[7:0}) | (selectorEven & ({a[7:0] - b[7:0]}));

you used wrong {} and [], {} used to concatenate the bits. It should be fixed like this:

assign {cout,out} = selectorOdd ? (a + b) : (selectorEven ? (a - b) : {9{1'b0}});

Your code should have more the case for else all. In this code if selectorOdd and selectorEven are 0, I assign {cout,out}={9{1'b0}}.

Problem with Verilog Dataflow testbench causing different errors on different sites

1 Answers