How to use vector operations in RISC-V Assembly

1
votes

I am trying to exploit vector operations in RISC-V Assembly, in particular I need to compile my source code with arch RV64iV or RV64GV. I am using riscv64-unknown-elf- toolchain, with the following parameters:

riscv64-unknown-elf-gcc -o test -march=rv32iv test.s

but I get the following error:

Assembler messages: Fatal error: -march=rv32iv: unsupported ISA subset `v'

Thanks

2
assemblysimdriscv
Try to update your toolchain. – fuz
This post about RISC-V Vector Extensions from September 2018 says that "At present there has been no implementation work or experimentation conducted with GCC". – Michael
@Michael: But does that just mean no auto-vectorization or intrinsics that will get GCC to emit the instructions? GNU Binutils is a separate project and could have implemented the asm instructions even if gcc never emits them. (gcc on a .s just feeds the asm file to as from binutils. -march options are usually meaningless when only assembling, not compiling, but can matter on ARM for thumb vs. ARM... Probably not for RISC-V) – Peter Cordes
@PeterCordes: No idea. That was the information I could find. I haven't built binutils myself lately so I don't have any recent source distribution. – Michael
My comment was partly addressed at the OP: they should try riscv64-unknown-elf-gcc test.s and see what the assembler says, instead of erroring out the GCC front-end. – Peter Cordes

2 Answers

1
votes

As of February 2019 there is no standard RISC-V vector extension, which means there is no support in standard RISC-V toolchains. There are various drafts of the vector extension floating around, but nothing supported by software.

1
votes

As of early 2020, the RISC-V vector extension "V" specification is at version 0.8 and still has draft status.

However, there are "V" ports of the GNU gcc/binutils available and the Spike RISC-V simulator supports "V" 0.8, as well. The README of the "V" spec links to the relevant branches.

I recently published some notes on how to get started with RISC-V "V" 0.8 development, e.g. how to build the right toolchain, related components, assemble, compile "V" code and how to test it with Spike.