0
votes

i am trying to create a module which has other module of memory , I am trying to have one parameter which of array , and using this parameter following code will generate modules instance , now I am trying to instantiate this module with setting only one element of this parameter array of only one index

Now the below code will give you the idea what I have tried , but the compiler is giving an error as -- "" MEM_AT_CS is not an array""

/////////////////////////////////////////////////////////

typedef enum   {NONE , SSRAM_X16 , SSRAM_X32 , SDRAM_X8 , SDRAM_X16 , 
                SDRAM_X32 , SYNC , ASYNC} memory_config_type;

module MEM_MODEL_WRAPPER (mem_intf intf , input logic mc_clk);

  parameter no_of_chip_select = 8;
  parameter memory_config_type MEM_AT_CS[no_of_chip_select-1 :0] = 
         '{NONE ,NONE ,NONE ,NONE ,NONE ,NONE ,NONE ,NONE  };


  genvar i;

  generate
    for(i=0 ; i<no_of_chip_select;i++) begin    

       case(MEM_AT_CS[i]) 
       SDRAM_X8:begin       
             .
             .
             .

now top module

module top ;

  //////////here i want to set the parameter array by index 

  defparam mem_dut.MEM_AT_CS[2] = SSRAM_X16;

  MEM_MODEL_WRAPPER  mem_dut(mem_intf , mc_clk);

endmodule       

I have tried this too

MEM_MODEL_WRAPPER #( .MEM_AT_CS[2] (SSRAM_X16) ) 
                                    mem_dut(mem_intf , mc_clk);
2

2 Answers

0
votes

You cannot do it for a slice of the parameter. You need to set the whole array. Here is an example:

module M#(parameter int array[2] = '{1,2})();
   initial $display("%m {%0d,%0d}", array[0], array[1]);
endmodule // M

module top();
   M m1();

   M m2();
   defparam m2.array = '{3, 4};

   M #(.array('{5,6}))m3()   ;
endmodule // top
0
votes

SystemVerilog does not allow for partial parameter array (ie, just assigning a single index of a parameter array). You can only assign the entire array all at once:

MEM_MODEL_WRAPPER #(.MEM_AT_CS('{NONE, NONE, SSRAM_X16, NONE, NONE, NONE, NONE, NONE})) mem_dut(mem_intf , mc_clk);