Individual binding for unpacked array elements in SystemVerilog

Question

In synthesizable SystemC I can bind each element of vector of ports individually:

SC_MODULE(submodule)
{
    sc_vector<sc_in<int> >  SC_NAMED(in_vec, 3);  
};

SC_MODULE(top) {
    submodule               SC_NAMED(submod_inst);
    sc_signal<int>          SC_NAMED(a);
    sc_signal<int>          SC_NAMED(b);
    sc_signal<int>          SC_NAMED(c);

    SC_CTOR(top) {
        submod_inst.in_vec[0].bind(a);
        submod_inst.in_vec[1].bind(b);
        submod_inst.in_vec[2].bind(c);
    }
};

Is there a way to do the same in synthesizable SystemVerilog?

module submodule (
    input logic[31:0]   in_vec[3];
);

endmodule

module top ();

    logic [31:0] a;
    logic [31:0] b;
    logic [31:0] c;

    submodule submod_inst (
//        What should I put here?
//        .in_vec[0] (a),  /// ERROR!!
//        .in_vec[1] (b),
//        .in_vec[2] (c)
    );


endmodule

Enze Chi Enze Chi · Accepted Answer · 2018-11-16T20:22:39

Have you tried

.in_vec('{a, b, c})

Or you can create a array and assign individual value to it. Then bind the array signal to sub module.

Individual binding for unpacked array elements in SystemVerilog

1 Answers