Can I use a variable inside a generate statement?

Question

I am wondering if it is possible to use a variable inside a generate statement.

signal bitmap_nodes : std_logic_vector(0 to NB_NODES-1) := (others => '0');

CIRCULAR: if (CLOCKWISE = 0) generate
    variable index : integer := 0;
    begin
    GENERATE_NODE : for i in NB_NODES-1 to 0 generate
    begin        
        node_inst: node
        port map (                    
            rx_bitmap => bitmap_nodes(index)
        );

        -- Increment index
        index := index + 1;

    end generate GENERATE_NODE;

end generate CIRCULAR;

Here, the variable is only used for the vector slicing. What it will do is assign the following (assume NB_NODES equals 4):

NODE0 -> bitmap_nodes(3)
NODE1 -> bitmap_nodes(2)
NODE2 -> bitmap_nodes(1)
NODE3 -> bitmap_nodes(0)

Martin Thompson Martin Thompson · Accepted Answer · 2011-03-15T14:37:25

That seems to be the same as:

   LAST: if (i = 0) generate
            firstnode : node
            port map (
                rx_bitmap => bitmap_nodes(NB_NODES-1)
            );
        end generate LAST;

isn't it?

EDIT:

I'm still not clear why you'd like to do this, but you can (post-VHDL87) put a shared variable in this area (you can treat it much like the part between architecture and begin). Remember that shared variables have to be of a protected type if you're not going to have all sorts of problems with race conditions.

However, you can't increment a variable like you are doing as the generate statement has to be populated with concurrent statements (and variable assignments aren't).

Again, I'd be really interested to see an example where this functionality is necessary (or is it more of an academic question?)

Can I use a variable inside a generate statement?

1 Answers