I am facing an issue related to Return-From-Interrupt when the IRQ interrupted a load/store multiple instruction.
When the IRQ interrupts a load/store multiple instruction, the ICI field of EPSR indicates that the LDM/STM instruction should be continued on the return from interrupt.
On interrupt entry exception frame(containing caller saved context) is stored on the current stack automatically by the hardware.
In my case, Kernel Software then saves the Callee saved context and prepares a new context, which includes a dummy exception frame on the stack. After preparing the new context the BX LR instruction is executed which pops the dummy exception frame. As the dummy exception frame contains the return-address(return address is pointing to new interrupt handler), execution goes to new interrupt handler.
In this case, if the interrupted instruction was an LDM/STM instruction I get a USAGE-FAULT exception with INVSTATE, because hardware on return-from-interrupt is expecting the appropriate LDM/STM instruction, while the return address is a different location in my case.
The ARM-Architecture Reference Manual mentions three design options that can be implemented for CortexM.
In the Instruction Set Attribute Register 2(ID_ISAR2), bits[11:8]:
- None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M reserved.
- LDM and STM instructions are restartable.
- LDM and STM instructions are continuable.
My hardware is implemented with option 3.
What I am unable to understand is, if I force the ICI field of IPSR to 0, will my LDM/STM instruction be restarted or will I still get an exception?
And even if it gets restarted(considering the interrupted STM instruction) will it push on top of already partially pushed registers, corrupting the stack eventually in this case or will it adjust the stack pointer before restarting the operation.