How JTAG debugger able to stop watchdog timer

Question

I am working on a project where I connect JTAG to SOC and debug the image on the SOC using the JTAG. The image also runs with watchdog timer that runs during core initialization, and which needs to be reset periodically to prevent the board being reset.

Now for my own understanding I was wondering how JTAG connects to the image and lets us set breakpoint during initialization without worrying about the watchdog timer. I have seen the image running for a long time, under JTAG, without the board being reset by watchdog.

I tried talking to multiple people in my team to try understand this but none of the explanations were satisfactory. Can somebody please explain what exactly is going on in terms of both JTAG and watchdog timer.

Answer 1

The answer depends on the type of SoC you are debugging since the watchdog function normally is an independent function inside or outside the SoC, and I don't see a direct relation to the JTAG interface of the CPU.

Still, some controllers do implement features to stop the watchdog time while the CPU is stopped by a breakpoint. For example, STM32F1 controllers offer the DBGMCU_CR register where you can (even through the debugger) configure whether the watchdog timer shall continue running while the core is halted.