how does systemverilog argument passing value work?

Question

Now I'm analyzing the UVM code as below for studying.

 // UVM run_phase()
task run_phase(uvm_phase phase);
  forever begin
    // send the item to the DUT
    send_to_dut(req);
  end
endtask : run_phase

task send_to_dut(uart_frame frame);
  
    
endtask : send_to_dut

But I'm confused that how send_to_dut(req)'s req argument can pass to the send_to_dut(uart_frame frame)'s uart_frame frame? It's quite confusing.

req --> uart_frame frame

Answer 1

It works because the value in this case is a class handle. And a handle is a reference to a class object. So you are passing a reference by value. See this link for more details