arm gcc assembly inline with FPU register

Question

I want to use FPU instruction of Cortex-M7, called VCVTR, to convert a double precision floating number to an integer.

int double_to_int(double value)
{
    int result;
    __asm("VCVTR.S32.F64 %0, %1" : "=r"(result), "r"(value));
    return result;
}

But I get error information from the compiler.

Error: VFP single, double or Neon quad precision register expected -- `vcvtr.s32.f64 r3,r3'

How to fix this problem.

Maybe the constraint "=r" and "r" is not correct. But I don't know other constraints for FPU registers.

My compiler is arm-none-eabi-gcc, version is 7.2.1

My compiler option is

-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -O3 -g -munaligned-access

Please read the documentation for extended assembly. On this page it tells you what constraints there are. — fuz

Jester Jester · Accepted Answer · 2018-08-22T11:35:10

For starters the compiler is perfectly capable of generating that instruction. Not only capable, but in fact a simple return value produces that. Nevertheless, the constraints are documented in the manual. In particular:

t VFP floating-point registers s0-s31. Used for 32 bit values.

w VFP floating-point registers d0-d31 and the appropriate subset d0-d15 based on command line options. Used for 64 bit values only.

Also you accidentally specified two output constraints. value should of course be an input.

arm gcc assembly inline with FPU register

1 Answers