hierarchical compile order with modelsim on command line

1
votes

I'm trying to compile a VHDL design with modelsim on command line. Is there any way to get an automatical compile order according to the design hierarchy?

I didn't find an option in the documentation of vcom. Only link I found is this, where the solution was to write a brute force script. But it's 10 years ago, so maybe there is anything new. It should be like the option -i of ghdl.

I'm using Altera/Intel Modelsim 18.0 on Linux.

1
vhdlmodelsim
ghdl -i (import) imports specified VHDL files into the working library without analysis. ghdl -m configuration_or_entity_target (make) analyzes them in the correct order and elaborates the passed design unit name. ghdl also has an internal makefile generator (--gen-makefile) that outputs the text for a makefile, with import ordered dependencies for elaborating a target. ghdl --gen-depends will output file dependency without the complete makefile text. See Invoking GHDL. - user1155120
You are right. I confused -i with -m. If there isn't an option to get the dependencies directly via vcom command, I will try to use the workaround with ghdl --gen-depends. - Marph
Take a look at this ModelSim Compile Script. I didn't try it but it might help - grorel

1 Answers

0
votes

VUnit is an open source tool that will that for you. I recommend the following reading

  1. Installation
  2. Compilation (what you're looking for)

Disclaimer: I'm one of the authors