Redundant IRQ clear-pending operation

0
votes

I am working on a project with ARM Cortex-M0 processor. In this project I need to provide timers support (CMSDK (SSE-200) timers).

So, in the vector table, in the proper entry represented by TIMER0_IRQn we placed our handler timer0_irq_handler, which contains the following code:

void timer0_irq_handler(void)
{
    NVIC_ClearPendingIRQ(TIMER0_IRQn)
    my_timer_irq_handler(TIMER0)
}

My question is whether or not the call to NVIC_ClearPendingIRQ is needed, because from Cortex-M0 Devices Generic User Guide:

A pending interrupt remains pending until one of the following:

The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active.

To my understanding, it means that the interrupt pending state is cleared automatically when we enter our ISR, and probably the call to NVIC_ClearPendingIRQ is redundant. Is it?

1
carminterruptinterrupt-handlingcortex-m

1 Answers

0
votes

It is cleared automatically.
You can check if it is pending, with NVIC_GetPendingIRQ().