NVIC User Interrupt Priority

Question

Im using FreeRTOX V9.0.0 on a Cortex M3 (Silicon Labs EFM32GG380F1024). I get a assert failure when i use the TaskResumeFromISR via the GPIO Irq Handler.

The assert fails here in port.c (GCC ARM CM3) in function "void vPortValidateInterruptPriority( void )" on line "configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );" The values are: ucCurrentPriority is 0 and ucMaxSysCallPriority is 160.

// NVIC CORTEX M3
#define configPRIO_BITS 3

// FreeRTOS Config
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ( 0x05 )
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )

// port.c
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; // ( ( 0x05 ) << (8 - ( 3 )) ) & 224 = 160

In the user code, when i read the interrupt priority (where i currently use default "0") i get all interrupt priorities are zero except the 2 that are set up by the kernel (PendSV and Systick) which are 7.

// user code
prio = hal::nvic::getPriority(NonMaskableInt_IRQn); // =0
prio = hal::nvic::getPriority(HardFault_IRQn); // =0
prio = hal::nvic::getPriority(MemoryManagement_IRQn); // =0
prio = hal::nvic::getPriority(BusFault_IRQn); // =0
prio = hal::nvic::getPriority(UsageFault_IRQn); // =0
prio = hal::nvic::getPriority(SVCall_IRQn); // =0
prio = hal::nvic::getPriority(DebugMonitor_IRQn); // =0
prio = hal::nvic::getPriority(PendSV_IRQn); // =7
prio = hal::nvic::getPriority(SysTick_IRQn); // =7
prio = hal::nvic::getPriority(GPIO_EVEN_IRQn); // =0
prio = hal::nvic::getPriority(GPIO_ODD_IRQn); // =0
prio = hal::nvic::getPriority(USART1_RX_IRQn); // =0
prio = hal::nvic::getPriority(USART1_TX_IRQn); // =0
prio = hal::nvic::getPriority(LETIMER0_IRQn); // =0
prio = hal::nvic::getPriority(RTC_IRQn); // =0
prio = hal::nvic::getPriority(BURTC_IRQn); // =0

As soon as i define my interrupt priority 7 or higher, i have no more trouble.

When i now define each priority for each interrupt, what values can i use (where lower is higher priority and i should go bigger than 7 since my interrupts should have lower prio than the kernel).

So should i start at 8 and go up until where??

Thank you

Realtime Rik Realtime Rik · Accepted Answer · 2018-05-23T07:10:23

The lower the interrupt priority number the higher the actual priority. So 0 is the highest priority.

I think on the EFM32GG there are only 3 priority bits so priorities available are 0 to 7. (If there are 4 priority bits the available priorities are 0 to 15).

This priority bits are left shifted into the top bits. Therefore the available priorities are:

0 << 5 (0) - Highest.
1 << 5 (32)
2 << 5 (64)
3 << 5 (96)
4 << 5 (128)
5 << 5 (160)
6 << 5 (192)
7 << 5 (224) - Lowest

Sometimes the 5 unused bits are padded with zero's. So for example 224 is the same priority as 255 as the lowest 5 bits make no difference to the operation of the processsor (however they will affect the asserts).

You cannot make FreeRTOS API calls from interrupts that have a higher priority than configMAX_SYSCALL_INTERRUPT_PRIORITY. However you can change the value of this to suit your needs.

NVIC User Interrupt Priority

1 Answers