conditional jump and flag bit in assembly

Question

I'm studying assembly language. I understand that CMP R1 R2 operation sets flag bits(Carry, Overflow, Zero, Sign etc..)according to the result of R1-R2. And I understand that conditional jump instructions JXs such as JA, JBE follows after CMP. If flag bit condition is matched, JX instruction make IP jump to specified address.

What I never undetstand is "Tested Conditions" in the picture I attached.

CMP R1 R2

JAE somewhere

Above code obviously jump to somewhere if R1 is bigger or equal to R2. If R1=0111 and R2=0110, a JAE jump to somewhere. In this case,

R1-R2 = 0111-0110 = 0111+1010 = 10001 = 0001 with carry bit set

note that I added 2's complement of 0110 instead of subtracting 0110 because microcontrollers calculate in this way as I know

But textbook says that the JAE will jump if Carry flag is 0. My calculation show that C=1 if R1 is bigger than R2. Another examples show that C=1 if R1 is bigger than R2. There's no issue with sign.

So what's wrong with "tested conditions"?

Nothing. If R1 is greater than or equal to R2 there will be no need to borrow when subtracting R2 from R1, so the carry bit is clear. — David Hoelzer
Why do you calculate 111-110 by using addition and negating the second argument, and deduct the flags state from that addition? The CF & other flags are relevant to the subtraction, doesn't matter if internally it is done by addition of negated value, and 111-110 is 1 with CF=0, ZF=0, PF=0, etc... — Ped7g
@Ped7g As I know,there is no subtractor in microprocessor. So it takes 2's complement and add it by adder. — hskim
Subtraction is not the same as addition of 2's complement, because the resulting flags are different as you saw. — interjay
When using jae you're looking at numbers as unsigned. So adding the 2's complement of a number is not the equivalent as subtracting the original number. That is why the flag results are different. In your example 7 - 6 is not the same as 7 + 10 (it's 10, not "-6"). — lurker

old_timer old_timer · Accepted Answer · 2018-04-11T15:27:42

This subtraction

R1-R2 = 0111-0110

gets implemented like this in logic

     1
  0111
+ 1001
========

finish the math

 11111
  0111
+ 1001
========
  0001

so carry out (unsigned overflow) is a 1, signed overflow is a 0 as the carry in and carry out to the msbit match can also determine this from the msbits of the operands and the result. if the msbits of the operands match each other but the msbit of the result doesnt match the msbits then signed overflow.

not zero so a z flag would be 0, and the msbit is not set so an n flag would not be set.

the next question is does this architecture invert carry out into the carry flag on a subtract making it a borrow or do they take it straight across?

In any case you have your four basic flags, carry, signed overflow, negative and zero. With good documentation you get a list of flags for the condition. You kind of know in your head if you want a greater than or less than or whatever, this little pencil and paper test, along with doing it on the processor and dumping the flags to see if this architecture inverts the carry out, also reading the docs to see if all the flags are touched by the test instruction in question, then looking at the various tested conditions to see which ones match your result.

conditional jump and flag bit in assembly

1 Answers