SystemVerilog: difference between @(posedge clk) and ##1

0
votes

In a SystemVerilog testbench, what's the difference between using @(posedge clk) and ##1 to wait until the next rising clock edge?

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system-verilog

1 Answers

2
votes

There are fewer places you can use ##1 because you need to setup a default clocking block context. This prevents you from using ##1 as a delay in any code declared in a package, like it would be in a class-based testbench using UVM. ##N is functionally equivalent to repeat(N) @(clocking_block_name) except when N is 0. ##0 blocks until there is a clocking block event and does not block if there has already been a clocking block event in the current time slot.