performance of single-cycle processor

1
votes

Given:

  1. Operation time required by:

    • memory units: 200 ps
    • ALU and adders: 100 ps
    • Register file: 50 ps
    • other units and wires: no delay

  2. Instruction mix and operation time in ps:

    • 25% loads (600 ps)

    • 10% stores ( 550 ps)

    • 45% ALU instructions (400 ps)

    • 15% branches (350 ps)

    • 5% jumps (200 ps)

  3. Every instruction executes in 1 clock cycle

  4. Two implementations: fixed length and variable length

Which implementation would be faster and by how much?

Solution

Reference Table

Rule: CPU execution time: IC * CPI * CCT

Since CPI = 1...

CPU execution time: IC * CCT

My questions are:

  • What does it mean when an implementation has variable / fixed length?

  • How were the values for CPU execution timesingleclock calculated?

1
performancecpucomputer-sciencecpu-architecture
Fixed-length what? Maybe instructions, i.e. every instruction is 32-bits, and aligned on a 32-bit boundary? Or pipeline length if you're considering design changes? But when you say Every instruction executes in 1 clock cycle, I think you mean not pipelined, and fetch/decode/execute/write-back all happen in one (slow) clock cycle, maybe with a faster clock to drive internal circuitry? Or does that just mean that ALU instructions always have 1-cycle latency? - Peter Cordes
@PeterCordes not really sure fixed-length what. and yes, single clock cycle, in this context, means not pipelined - user9548324
Oh, the solution says fixed vs. variable clock period. I guess in a variable-clock system, the CPU would generate the clock itself, so instructions could take different amounts of real time but still be a single clock period, because the rising or falling edge of the clock signal doesn't happen until the CPU is done executing the instruction. That's pretty weird, and makes a mockery of usual performance metrics like cycles per instruction. - Peter Cordes

1 Answers

1
votes

What does it mean when an implementation has variable / fixed length?

Fixed length clock means that each clock cycle has the same period, irrespective of the instruction being execution. Variable length clock means that different clock cycles may have different periods, depending on the instruction being executed.

So in a fixed clock design, the clock cycle has to be at least 600 ps, which is the longest time any instruction would take to execute (the load instruction). In a variable clock design, we can calculate the average clock cycle as follows:

Average CPU clock cycle = 600*25% + 550*10% + 400*45% + 350*15% + 200*5% = 447.5 ps

How were the values for CPU execution timesingleclock calculated?

To determine which implementation is faster, you need to measure speedup, which is defined as:

Speedup = CPU execution time(single) / CPU execution time(variable)

Using the definition of CPU execution time we get (note that the number of instructions is the same):

Speedup = CPU execution time(single) / CPU execution time(variable)
        =  (Instruction count * Clock cycle time(single)) / (Instruction count * Clock cycle time(variable))
        = Clock cycle time(single) / Clock cycle time(variable)
        = 600 / 447.5 = 1.34

Se the variable clock design is 1.34 faster.

Regarding CPU execution timevariable

CPU execution timevariable is technically equal to the sum of the individual clock cycle times of each executed instruction. But we used the average clock cycle time instead to calculate speedup. Will we get the same result either way? Let's find out!

Assume there are N executed instructions and let C1, C2, ..., CN denote the cycle times of each of them, respectively. Hence:

CPU execution time(variable) = C1 + C2 + ... + CN
                             = 600*25%*N + 550*10%*N + 400*45%*N + 350*15%*N + 200*5%*N
                             = N * average CPU clock cycle

So they are the same.