Creating Demux in Verilog

Question

Hello I have a homework about verilog.

My task is :

''When interrupt is asserted, s1 register will give the counter number of interrupt in interrupt subroutine. When more than one interrupt is received, s1 register will give output of priority encoders.''

The schema :

I designed the schema and saw in verilog RTL Schematic except demux part. How can I see demux part together with other part?

Here is my verilog top_module code. counter ,priority encoder,picoblaze is given to me.

I tried to write orgate part and demux .

    module top_module(
input clock,
input reset
);


 ///////priority_encoder///////
 wire [3:0] encoder_in;
 wire [2:0] encoder_out;

 ///////////////////////////

 /////picoblaze//////
 wire interrupt_ack;
 //////////////////////////

 //////coder/////////////
 reg start1;
 reg start2;
 reg start3;
 reg start4;
 ///////////////////////



 always @ (encoder_out or interrupt_ack )
 begin
        case(encoder_out)

        3'b001:
        start1 <=1'b1;
        3'b010:
        start2 <=1'b1;
        3'b011:
        start3 <=1'b1;
        3'b100:
        start4 <=1'b1;

        endcase
 end

 ascode instance_name (
.address(address), 
.instruction(instruction), 
.clk(clk)
);

 kcpsm3 picoblaze (
.address(address), 
.instruction(instruction), 
.port_id(port_id), 
.write_strobe(write_strobe), 
.out_port(out_port), 
.read_strobe(read_strobe), 
.in_port(encoder_out), 
.interrupt(interrupt), 
.interrupt_ack(interrupt_ack), 
.reset(reset), 
.clk(clk)
);

 priority_encoder p_encoder (
.encoder_in(encoder_in), 
.encoder_out(encoder_out)
);

 counter c100 (
.clk(clk), 
.start(start1), 
.count_up_to(100), 
.ready(encoder_in[0])
);

counter c200 (
.clk(clk), 
.start(start2), 
.count_up_to(200), 
.ready(encoder_in[1])
);

counter c300 (
.clk(clk), 
.start(start3), 
.count_up_to(300), 
.ready(encoder_in[2])
);

counter c400 (
.clk(clk), 
.start(start4), 
.count_up_to(400), 
.ready(encoder_in[3])
);

 orgate orgate (
.r1(encoder_in[0]), 
.r2(encoder_in[1]), 
.r3(encoder_in[2]), 
.r4(encoder_in[3]), 
.y(interrupt)
);



endmodule

Oldfart Oldfart · Accepted Answer · 2018-04-01T08:31:53

You will not see the demux as it is optimized way. Your code always produces a 1.

You probably want this:

always @ ( * )
begin
    {start1,start2,start3,start4} = 4'b000;
    case(encoder_out)
    3'b001 : start1 =interrupt_ack ;
    3'b010 : start2 =interrupt_ack ;
    3'b011 : start3 =interrupt_ack ;
    default: start4 =interrupt_ack ;
    endcase
end

As you see I used always @(*). It is safer.
Your start signals are default set to zero.
You have a combinatorial block and thus must use blocking assignment.
For some reason you use 3 encoder out bits, thus you MUST decode all states otherwise you get latches. That is what the default is for.
By keeping repeated code compact you can better see regular patterns. In this case I see that you start with 3'b001 not with 3'b000 for some reason.

Creating Demux in Verilog

1 Answers