Syntax to check whether the data is right or not (systemverilog)

Question

I wanna create the task that verifies the output is correct or not. If it is correct it shows correct +1 and if there would be an error it shows error +1. By writing this code, I couldn't get any value in expected123.

logic [31:0] expected123;
task checker123 (logic [31:0] expected, logic [31:0] actual, bit [3:0] command, logic[31:0] input1, input2);
  $display("%h, %h, %h, %h, %h", expected, actual, command, input1, input2); 

  if(command == "0001")
    expected123 = input1 + input2;
  $display(expected, input1, input2);

  if(command == "0010")
    expected123 = input1 - input2;
  $display(expected, input1, input2);

  expected = expected123;

  if (expected !== actual) begin
    $display("%t: command %h is expected %h but got %h ", $time, command, expected, actual);
    error = error + 1;
  end
  correct = correct + 1;
endtask

to instantiate this task checker123(expected123 , topif.cb.out_data3, ADD,add1.a, add1.b); where topif.out_data3 is actual output by circuit, add = 0001, add1.a and add1.b are random inputs generated by random. I'm confused expected123. Is that okay to force this? any suggestions? — user9526404
you are comparing 4-bit binary command with an 64-bit string "0001". this is not verilog. — Serge
Please read Under what circumstances may I add “urgent” or other similar phrases to my question, in order to obtain faster answers? - the summary is that this is not an ideal way to address volunteers, and is probably counterproductive to obtaining answers. Please refrain from adding this to your questions. — halfer

dave_59 dave_59 · Accepted Answer · 2018-03-21T05:42:49

You might be inadvertently writing VHDL syntax in Verilog. Should be

  if(command == 4'b0001)

Syntax to check whether the data is right or not (systemverilog)

1 Answers