Verilog signed multiplication

Question

I have a question about multiplication. In my case, row and vec are my inputs. Each contains N signed numbers with DW data width. temp1 and temp2 are arrays used for storing multiplication result. All numbers are signed. The question is why temp1 and temp2 got a different answer? why temp1 wrong but temp2 correct? Sorry, I'm new in Verilog and can't figure out why. Thanks!

input signed [(DW * N) -1 : 0] row;
input signed [(DW * N) -1 : 0] vec;
always @(*) begin
  for (i=0;i<N;i=i+1) begin
    t1 = row[i*DW +: DW];
    t2 = vec[i*DW +: DW];
    temp1[i] = t1 * t2;
    temp2[i] = (row[i*DW +: DW] )* (vec[i*DW +: DW]);
  end
end

can you check if you have declared t1 and t2 are declared as signed wires ? — badri18

dave_59 dave_59 · Accepted Answer · 2018-02-15T08:27:34

2

votes

A part-select of any vector is unsigned, regardless of whether the whole is signed.

Verilog signed multiplication

1 Answers