Is initial synthesizable in ASIC?

0
votes

I haven't tried to synthesize myself but if someone could help to give a quick answer, that would be highly appreciated.

For a regular RAM, I see people do this in their Verilog, but I am told that initial is not synthesizable in Synopsys Design Compiler and I wonder if there is a difference among tools. Or this is doable just for memory initialization.

initial begin
    for (count=0;count<2048;count=count+1) RAM[count]=0;
end

This is specifically targeting ASIC instead of FPGA or Xilinx. Thanks in advance!

1
verilogsynthesis
Instead of using initial block, one can also initialize memory by using reset condition in always procedural block. – sharvil111
@sharvil111 can I reside for loop with reset? – user3431800
Yes as far as the for loop terminating condition is fixed. If you are using SystemVerilog, then one can also use default array assignment '{default:'0}. – sharvil111

1 Answers

1
votes

No, it can be used for simulation purposes only. Synopsys Design Compiler does not synthesize initial blocks, it throws the following warning instead.

The statements in initial blocks are ignored.