system verilog expect behavior

Question

I tried using expect with the following property

module tb;

logic a;
logic clk=0;

default clocking @(posedge clk); endclocking

always
  #5ns clk = ~clk;

initial begin
  $dumpfile("dump.vcd"); $dumpvars;
  $display("START");
  a = 0;
  #100ns;
  a = 1;
  #100ns;
  $finish;
end

initial begin
  #10ns;
  expect(@(posedge clk) 1 ##1 $changed(a) |-> 1) $display("SUCCESS"); else
$display("FAIL");
end

endmodule

Is the expect going to block until a change from 0 to 1 at 100ns ?

With the tool I'm using (irun) you need to define default clocking block in order to compile it. I don't know for the other tools — Viktorinox
It also doesn't compile for me. Can you please share your actual code? I have also tries with default clocking block — Karan Shah
You can use the following eda link : edaplayground.com/x/2nvM — Viktorinox

dave_59 dave_59 · Accepted Answer · 2018-01-24T14:57:41

No, it will block until the second (posedge clk), regardless of the value of a, and will always pass.

The expect statement does not start evaluating the property until the first clk edge. The antecedent takes two cycle to either match or not match. Since the consequent is always true, the property passes on match. If there is no match, the property also passes, vacuously.

system verilog expect behavior

1 Answers