No rule to make object files based on pattern

Question

Hello I am trying to build my C++ project. I currently have a makefile that lists out all the names of the .o files I want to make. Then I prefix the directory onto them where I want them to be compiled to. Finally, I have two basic rules that handle building each object file then the executable from those object files. For whatever reason, make is not recognizing the pattern. Here is the makefile

CXX=g++
SRC_DIR=/home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/lib
INC_DIR=-I/home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/include
INC_DIR += -I/home/epi/jfrye_xilinx/SystemC/systemc-2.3.2/include

LIB_DIR=-L/home/epi/jfrye_xilinx/SystemC/system-2.3.2/lib-linux64
LIB_TAGS=-lsystemc

OBJ_DIR=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/obj

ZYNQ_DEMO=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynq_demo
ZYNQMP_DEMO=/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynqmp_demo

OBJS+ = memory.o trace.o debugdev.o demo-dma.o xilinx-zynq.o xilinx-zynqmp.o
OBJS += safeio.o remote-port-proto.o remote-port-sk.o remote-port-tlm.o
OBJS += remote-port-tlm-memory-master.o remote-port-tlm-memory-slave.o
OBJS += remote-port-tlm-wires.o

_ZYNQ_OBJS=zynq_demo.o
_ZYNQMP_OBJS=zynqmp_demo.o

_ZYNQ_OBJS += $(OBJS)
_ZYNQMP_OBJS += $(OBJS)

ZYNQ_OBJS=$(addprefix $(OBJ_DIR)/, $(_ZYNQ_OBJS))
ZYNPMP_OBJS=$(addprefix $(OBJDIR)/, $(_ZYNQMP_OBJS))

$(info $(ZYNQ_OBJS))

all: $(ZYNQ_DEMO) $(ZYNQMP_DEMO)

$(ZYNQ_DEMO): $(ZYNQ_OBJS)

$(ZYNQMP_DEMO): $(ZYNQMP_OBJS)

$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
    $(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $@ $<

I am getting the error:

make: *** No rule to make target /home/epi/jfrye_xilinx/Cosimulation/Adder_PL/obj/zynq_demo.o', needed by/home/epi/jfrye_xilinx/Cosimulation/Adder_PL/bin/zynq_demo'. Stop.

The fourth rule should take care of zynq_demo.o correct. Why is it not recognizing a rule it can use to build that object file?

The easier way is using $(vpath) and not to specify the source directories explicitly at all. — user0042
Do you have a corresponding .cc file in the source directory, /home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/lib? — R Sahu
no, that was the problem. I was not aware that it would complain about no rule even if it could find the target file name in the list — John Frye
Did you really mean to write OBJS+ = memory.o... in your makefile? Not a syntax error, but not what you want either. — bobbogo

bobbogo bobbogo · Accepted Answer · 2017-12-29T15:44:03

I'm not a fan of pattern rules. When and where they apply is a little haphazard for my tastes. A better alternative IMHO is static pattern rules. To use these simply prefix your pattern rules with the targets that those patterns apply to.

So

$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
    $(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $@ $<

simply becomes

${ZYNC_OBJS}: $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cc
    $(CXX) $(INC_DIR) $(LIB_DIR) $(LIB_TAGS) -c -o $@ $<

I can't tell because I don't have your source tree, but I suspect make will now give you a different error. Something about /home/epi/jfrye_xilinx/Cosimulation/SystemC/Xilinx/lib/zynq_demo.cc being missing maybe (???).

No rule to make object files based on pattern

1 Answers