When is the status register updated in the 6502?

2
votes

I am currently developing a subset of the 6502 in LogiSim. One of my main resources is Hanson's Block Diagram.

I am trying to determine how and where I should build circuitry to update the Processor States Register. In the diagram of the Processor Status Register below, there are multiple control lines going into the register, but there is no indication of where they come from.

confusing part of the diagram

When and where is the 6502 Processor status register updated? I would think that it is on the output of the ALU, but I want to make sure that this is the case.

2
processor6502

2 Answers

8
votes

Do you have Hanson's complete updated diagram? The paper is here. (Or original here.)

The inputs on the left side of P (DB0/C etc) are outputs from the bottom of the Random Control Logic block. The inputs at the top of P are from the ALU (ACR, AVR) and IR5 is bit 5 of the Instruction Register. (But from Breaknes below it seems Hanson's diagram is incomplete: "Donald missed the 0/V command on the schematic, which is used when processing the CLV instruction.")

The inputs will be latched differently for various instructions. For instance the two cycle instructions like CLC/SEC/CLD/SED/CLI/SEI/CLV have one bit (IR5) that ends up latching a hard-coded value to only one of C, I, V, or D. Other instructions will latch ALU (etc) signals to multiple flags at a later cycle. That's as much detail as I know, and as much of the logic that will fit into an answer here.

Very detailed information is available at the Russian Breaknes site. The author has reverse engineered all of the 6502 logic at the transistor level from images at Visual6502. Have a good look around in the Wiki and Info sections of the site. E.g. here is a translated link to the flag info page which has a logic diagram, unlike the wiki page on flag logic.

There was a lot of discussion in the 6502 forum when he did this work (flag logic on page 12 and page 15) and some of the content might only be linked from this thread. The original code repo has been moved to GitHub where there is emulator source code and Logisim circuit diagrams.

4
votes

From the top:

The C flag is set or cleared by

  • any instruction that can have an unsigned overflow. These include ADC SBC, CMP, CPX, CPY
  • Shift and rotate instructions ASL, ROL, ROR
  • explicit set and clear instructions SEC, CLC
  • instructions that load the whole status register PLP, RTI

Z is set or cleared by

  • any instruction that writes to A, X, Y e.g. arithmetic as for carry, bitwise logical operations, loads, transfers, pulls from the stack, shifts and rotates.
  • instructions that load the whole status register PLP, RTI
  • BIT

I is set or cleared by

  • the SEI and CLI instructions.
  • instructions that load the whole status register PLP, RTI
  • set by BRK and interrupts.

D is set or cleared only by the PLP, RTI, SED and CLD instructions.

B is interesting. It's actually completely inaccessible to the programmer and not used by the processor. The status byte pushed on the stack is set for BRK and cleared for an interrupt. I guess that means that RTIand PLP would set it if it is set in the byte pulled off the stack, but it doesn't matter.

V flag is set or cleared by

  • ADC, SBC
  • BIT
  • instructions that load the whole status register PLP, RTI
  • CLV

N is set or cleared in the same circumstances as Z.

I would think that it is on the output of the ALU

That is a fair assessment for all the ALU ops, but as you can see from above there are circumstances when the status flags are set from a source other than the ALU.

Reference: http://www.e-tradition.net/bytes/6502/6502_instruction_set.html