SystemVerilog: $urandom call inside conditional expression

0
votes

So I wanted to set some bits in a vector with some hard-wired probability when an event was triggered, so I did this: 

always @(some_event) begin
  err_byte[0] = ($urandom()&65535 < 85) ? 1'b1 : 1'b0;  
  err_byte[1] = ($urandom()&65535 < 85) ? 1'b1 : 1'b0;  
  //....etc

and my err_byte had always the value of 8'h00, even if this code was triggered several thousands of times (which should've been enough to set at least one bit to 1). When I declared an integer rndv and did this: 

rndv = $urandom()&65535;
err_byte[0] = (rndv < 85) ? 1'b1 : 1'b0;
rndv = $urandom()&65535;
err_byte[1] = (rndv < 85) ? 1'b1 : 1'b0;
//etc...

then it suddenly works. Now the question: what the hell is happening here? Am I not allowed to call system tasks inside conditional expressions?

1
verilogsystem-verilog

1 Answers

3
votes

Operator precedence. < is ahead of & so your first example could be written like this.

err_byte[0] = ($urandom() & (65535 < 85)) ? 1'b1 : 1'b0;

See the problem now?