Dual port RAM best practices?

Question

I have a setup with an FPGA acting as a dual ported RAM shared between a PC and a micro controller. There are fpga semaphores that protect the ram from simultaneous access so I can avoid reading data in the middle of an update. So far, I’ve been using a byte buffer with a fixed order that I am reading into some structs to pass data in each direction, updated at 100 Hz. This has worked well.

I will be expanding the size of the ram window between the two processors, and would like to be able to pass large files between them. Is there a standard set of techniques for using dual ported ram this way?

using structs across compile domains is a practice that generally results in failure. — old_timer
you can use two/some of the memory locations as one way mailboxes to pass control information then use the rest of the ram for data. — old_timer
you can treat the ram as a circular buffer (or two if bidirectional) where one side controls the head pointer (a location in ram) and the tail pointer (a location in this ram). the data itself would contain a header, length checksum/crc to convey what the data is. Depending on what you are doing all communication could be sent/received in this way. Or you could have special mailboxes that are for specific items and the circular buffer for other. — old_timer
You're right, of course. I should have said a byte buffer with a fixed order that I am reading into some structs. — carmiac

Gerhard Gerhard · Accepted Answer · 2017-11-14T07:07:22

If you have a FPGA implement a FIFO for each direction of communication between the two. This would mean file sizes and synchronization is no longer a hardware related problem. When your struct or file is packed have a DMA or interrupt handler transfer it over and visa versa. This will make you code simpler and more reliable.

If there is high rate data the will be blocked by a large file transfer you will need a high and a low priority FIFO.

Dual port RAM best practices?

1 Answers