How to implement Summation equation in SystemVerilog constraints?

0
votes

c=∑(a[i]*b[i]) Consider Two arrays a and b. The result,c of MAC operation of the two arrays a and b should be less than 1024. Use SystemVerilog constraints to implement above condition. Size of the two arrays can go from 1 to n and each array element stores 1 byte. We have to randomize both arrays.

1
system-verilog
Is this a homework question or an interview question? - dave_59
It is an interview question. - Rottenengg
I'll give you a hint then. Use the sum() with() method in a constraint. - dave_59
Thanks dave for the hint. My initial guess was to used a same method. But I am not able to write a method to randomize the each element of array with given constraint. Should I declare a function to implement summation equation and call that function inside the constraint block ? - Rottenengg
You can do your constraint using one sum() method. Any more hints will give away the solution. - dave_59

1 Answers

3
votes

Now that I've seen your solution in chat, I'll give you what I was thinking

constraint c_sum { c == a.sum() with (a[item.index] * b[item.index]); c < 1024;}