I am trying to compile the source code twice with a MACRO defined & undefined. So for default the macro is undefined & i want to define this macro through arguments from Makefile, like
$(MAKE) -c $(present_dir)/new_dir -DONE_MACRO=1
so i am using this ONE_MACRO
in file.h
.
how this definition is reflected and knows to preprocessor. Here im using cygmake
. How to pass an MACRO as argument to compiler
with cygmake tool.
file.h:-
#if ONE_MACRO
#define some_targets
#else
#define other_targets
#endif
So how this ONE_MACRO is defined from make file, im trying to pass macro as argument as below
Makefile:-
MY_TARGET:
$(MAKE) -C $(present_dir)/target_dir -D ONE_MACRO=1 $(MAKECMDGOALS)
#ifdef
withinfile.h
. Does that answer your question? – Beta-D MACRO_DEFINE=1
argument (conventionally written without the space between the option letterD
and the valueMACRO_DEFINE=1
) as if there was a line of code that read#define MACRO_DEFINE 1
. This is set before any of the actual code is processed. That's straight-forward, so it probably isn't what you're asking — but it isn't clear what you are asking. – Jonathan Lefflerfile.h
.so while compiling i'll compile thefile.h
twice based on the macro as defined & undefined. I think its clear now. – Kumar2080