Which stack is used when entering interrupt handler from user program for Cortex M3 processor?

3
votes

Cortex M3 processor has two stack pointer: PSP, MSP. In some complex applications, user program use PSP pointed to user program stack. Exception handler use MSP pointed to main stack.

The question is: There is a interrupt happened when user program is running. Before entering into the interrupt handler, the R0-R3, R12, LR, PC, and xPSR registers would be pushed into stack. But which stack is used to store these registers ?

1
armstackembeddedmicrocontrollercortex-m3
sometimes they have two stack pointers, not sure on the m3 but some of the cortex-ms it is a compile time option. And using the second stack pointer is painful at best, unless you are specifically trying to use it you are sharing one stack. trivial to see if you copy/dump the stack in a handler then examine it... – old_timer
Os use main stack, user program use program stack. Some simple application will only use MSP (main stack). – lrouter
The stack pointer, SP, banks SP_main and SP_process. The current stack depends on the mode and, in Thread mode, the value of the CONTROL.SPSEL bit, see The special-purpose CONTROL register on page B1-575. A reset selects and initializes SP_main, see Reset behavior on page B1-586. – old_timer
right there in the arm docs, will let you read the rest – old_timer
are you answering your own question or at least trying to? Confused. You cant always use the second stack, if you have ever tried to use it you may find out why you might not want to use it or more importantly it doesnt at all work like you think it does, and why are you asking this question if you already have an answer in your mind as to how it works? – old_timer

1 Answers

4
votes

According to my reading of the ARM documentation (Cortex-M3 Devices Generic User Guide), register stacking upon exception entry happens on the current stack and the processor then enters Handler mode. If you think about it, this is the most convenient behavior for ordinary circumstances.