chisel function on the left side of the assignment

1
votes

what I trend to do:

Cat( ...a list of inputs... ) := a wide wire of UInt

When I do this the scala reports syntex error about Bits, so I change it to:

Cat( ...a list of inputs... ).flatten := a wide wire of UInt

This time the scala satisfied but the firrtl reports error because the left side of the assignment will be assigned to a wire and then it violence with the input:

node _T_47 = bits(...one piece from the list which is a Input...)

_T_47 <= ... // this violence the (FE)MALE rule

Could you enlight me any other way to use func on the left side of the equation? Or Am I forbidden to use func in this way...

1
assignchisel

1 Answers

1
votes

You are correct that you cannot use the outputs of functions like Cat on the left hand side of connections.

Check out the Chisel3 Cookbook which discusses (and solves) this problem here: https://github.com/freechipsproject/chisel3/wiki/Cookbook#how-do-i-unpack-a-value-reverse-concatenation-like-in-verilog