What is the equivalent of 'Cache line size' in PCIE?

Question

In PCI configuration space, Cache line size indicates system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command.

The value in this register is also used by master devices to determine whether to use Read, Read Line, or Read Multiple commands for accessing memory.

Slave devices that want to allow memory bursting using cacheline wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the cacheline.

But this field is implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no effect on any PCI Express device behavior.

Then how PCIe system implements memory-write-invalidate feature ?

Answer 1

The PCIe has a supplement protocol that is called Address Translation Services (ATS), in this protocol, there is a description for invalidation (chapter 3). The bottom line is a MsgD Transaction Layer Packet (TLP) called Invalidate that can do that. Note that in general, it is completely separate (protocol-wise) from the MWr TLP.

Answer 2

As far as I know, PCIe does not have an explicit message memory write and invalidate. Instead, a root complex that recieves a write that happens to cover an entire cacheline can avoid reading that cacheline and invalidate it immediately.

I think in most cases you would simply generate MaxPayloadSize requests if possible, and hopefully also trigger this behaviour. If you must know the cacheline size from the device, I would suggest designing a device-specific mechanism, and configuring it from your driver.