Zynq-7000 by Xilinx. Interrupts system for AXI Uartlite

Question

I use Picozed SDR SOM 2x2. The version of my Vivado and SDK tools is 2015.4.

I need to use some PMOD connectors for axi_uartlite block.

After generating bitstream I has exported my hardware to SDK. Then I imported xuartlite_polled_example. Using oscilloscope and physical loopback from tx to rx I maked sure then example work well.

Then I imported xuartlite_intr_example (because there are important for me to use interrupts) and it don't work.

Some source for handling interrupts from example:

static volatile int TotalSentCount = 0;
static volatile int TotalReceivedCount = 0;

void SendHandler(void *CallBackRef, unsigned int EventData)
{
    TotalSentCount = EventData;
}

void RecvHandler(void *CallBackRef, unsigned int EventData)
{
    TotalReceivedCount = EventData;
}

The place where the program is catched at loop (checked with System Debugger and GDB) :

/*
 * Wait for the entire buffer to be received, letting the interrupt
 * processing work in the background, this function may get locked
 * up in this loop if the interrupts are not working correctly.
 */

while ((TotalReceivedCount != TEST_BUFFER_SIZE) ||
    (TotalSentCount != TEST_BUFFER_SIZE)) {
}

Why my interrupts are not working correctly? I tried also with Vivado and SDK 2016.4 and on the ZC702 board. Result the same, xuartlite_polled_example are working and xuartlite_intr_example are not.

Also I imported SDK examples for AXI Interrupt Controller and no one is working.

kilometrix kilometrix · Accepted Answer · 2017-10-13T13:31:12

Before any manipulations with code, you should check if AXI Interrupt Controller is connected to Microblaze processor directly. To do it quickly, you can check connections of Interrupt Controller in Graphical Design View (XPS). INTERRUPT port on Interrupt Controller must be connected to Microblaze' INTERRUPT port.

If they are not connected, interrupts will not work, obviously. But you can manually edit .mhs file of your project. For Microblaze and Interrupt Controller, add:

   # some ports...
   BUS_INTERFACE INTERRUPT = microblaze_0_interrupt
   # some ports...

Zynq-7000 by Xilinx. Interrupts system for AXI Uartlite

1 Answers