Using a testbench .vhd file in vivado

Question

I recently posted something with relation to this assignment but I have hit another stumbling block and can't seem to find the solution. I have got a 4 bit alu simulating but I am required to use a pre-written test bench provided to me by the teacher. I have imported the test bench file and un selected the check mark next to synthesis in the source file properties as instructed.

My unit under test as detected by the testbench source file is the entity .vhd file of my project and so all should be fine except that when I simulate the program it just simulates as per normal with no output in the tcl console regarding any of the assertions of which the testbench is composed.

I have obviously googled and got more instructions about how to do this but I couldn't get specific instructions for the vivado software. It talked about xilinx and there being a process window, which is nowhere to be seen in Vivado. I can't understand why this so seemingly simple thing is taking me so long to figure out. There aren't any syntax errors and it says in the messages near the compiler window that the testbench is being parsed. Here is a screenshot of my file structure in the vivado IDE.

Can anyone please tell me how to do this?

Thanks,

Simon.

You have selected the wrong top-level design unit (indicated by bold text) — Paebbels
In simulations sources section you should make your testbench as top-level module. In your case top-level module is alu — Roman

scary_jeff scary_jeff · Accepted Answer · 2017-04-10T10:14:54

When you simulate, it will use whatever is set as the top level simulation entity as the top level for that simulation. In your image, the test bench is selected in the project hierarchy, but the UUT is set as the top module. You need to right click your test bench, and choose 'Set as Top'.

Using a testbench .vhd file in vivado

1 Answers