verilog generate loop assign to iterator width mismatch

0
votes

I am using a generate loop to instantiate a paramaterizable number of modules, and I want to assign some of the inputs to the module based on the loop iteration. Unfortunately I'm running into issues with synthesis where design compiler says there's an error because the port width doesn't match. Here's what I'm trying to do:

genvar k;
generate
    for(k = 0; k < `NUM/2; ++k) begin
        cmp2 cmps(
            .a       (arr[k]),
            .b       (arr[k+1]),
            .a_idx   (k),   //gives errors about port width mismatch
            .b_idx   (k+1), //but I can't get it to work any other way
            .data_out(data[k]),
            .idx_out (idx[k])
            );
    end
endgenerate

I've also tried using localparams in the loop and assigning a_idx and b_idx to the localparam but I still get the same error under synthesis.

I've tried something like .a_idx((k)[bit_width-1:0]), but that doesn't work either.

Any ideas?

1
verilogsystem-verilogsynthesis

1 Answers

3
votes

k and k+1 are 32-bit wide, which causes the width mismatch. Depending on what your synthesis tool supports, you might want to try the following:

  • Bit slicing:

    .a_idx   (k[0 +: bit_width])

  • Cast to bit_width-wide logic:

    typedef logic[bit_width-1:0] logicN_t;
// .... //
  .a_idx   (logicN_t'(k)),
  .b_idx   (logicN_t'(k+1)),
// .... //