elaboration freezes when assigning variable x:= x + y

Question

I'm trying to create a booth multiplier for an academic project and I'm having the weirdest error. Not sure whether this traces back to Quartus II or something to do with VHDL.

Everytime I try to Analyse and Elaborate the following code, the process freezes indefinitely (I've had it run for an hour already) at 46% of the Analysis & Synthesis phase, in the console the last line is 12127 Elaborating entity "booth_mul" for the top level hierarchy without any other particular warnings or errors of note (just the usual (found x design units,...)

ARCHITECTURE booth_mul OF booth_mul IS
BEGIN
    process(Ain, Bin)
    variable result, toResult:      STD_LOGIC_VECTOR(63 downto 0);
    --other variables
    begin
    --other stuff
    for i in 0 to 31 loop    
    --other stuff
            --toResult is the partial product being added to the result
            toResult := STD_LOGIC_VECTOR(SHIFT_LEFT(UNSIGNED(toResult), i*2));
            result := result + toResult; --A&E Freezes if this line is included!!
        end loop;
        output <= result;
    end process;
END;

I've tried commenting out various parts of this and it's that line that is the problem. Is this a syntax problem with VHDL or with Quartus II itself?

using Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SJ Web Edition

Update: I've provided the rest of my code but it doesn't seem like it should be at fault. The design does compile without errors, but only after nearly three hours. Here is the full design:

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

ENTITY booth_mul IS
    PORT
    (
        Ain :   IN STD_LOGIC_VECTOR(31 downto 0);
        Bin :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
        output :  OUT  STD_LOGIC_VECTOR(63 DOWNTO 0)
    );
END booth_mul;

ARCHITECTURE booth_mul OF booth_mul IS
BEGIN
    process(Ain, Bin)
    variable result, temp, toResult:    STD_LOGIC_VECTOR(63 downto 0);
    variable toAdd, toSub : STD_LOGIC_VECTOR(31 downto 0);
    begin
        toAdd := Ain;
        toSub := (0 - Ain);
        for i in 0 to 31 loop
            if i = 0 then
                if Bin(0) <= '1' then
                    toResult(31 downto 0):= toSub;
            end if;
            else 
                if (Bin(i) <= '1' and Bin(i-1) <='0') then
                    toResult(31 downto 0):= toSub;
                elsif (Bin(i) <= '0' and Bin(i-1) <='1') then
                    toResult(31 downto 0):= toAdd;
                end if;
            end if;
        --  
        --  --Sign Extension
            if toResult(31) <= '1' then
                toResult(63 downto 32) := x"11111111";
            else
                toResult(63 downto 32) := x"00000000";
            end if;
            toResult := STD_LOGIC_VECTOR(SHIFT_LEFT(UNSIGNED(toResult), i*2));
            result := result + toResult; --A&E Freezes HERE!!
        end loop;
        output <= result;
    end process;
END;

Your question does not present a Minimal, Complete, and Verifiable example. — user1155120
I synthesised this on Quartus 13.1 web edition in 54 minutes on my 2014 i7 laptop. It's a lot of logic: 2082 logic elements. — Matthew Taylor
Do you have any VHDL experience? You're writing the code as if it was code for a CPU. VHDL (especially when for synthesis) requires a different approach. — JHBonarius

gsm gsm · Accepted Answer · 2017-02-20T02:38:47

I don't have access to any synth tools at work, so I'm speculating. However, you are trying to synthesise a completely combinational multiplier (I'm not sure if this is intentional or not), that is reasonably sized. I shudder at the resources required to implement that (and the resulting Fmax), which probably explains why the tool is taking so long.

elaboration freezes when assigning variable x:= x + y

2 Answers