Parallel Crc-32 calculation Ethernet 10GE MAC

3
votes

I have generated an Ethernet 10GE MAC design in VHDL. Now I am trying to implement CRC. I have a 64-bit parallel CRC-32 generator in VHDL.

Specification:
- Data bus is of 64-bits
- Control bus is of 8-bits (which validates the data bytes)

Issue:
Let's say, my incoming packet length is 14-bytes, (assuming no padding).

The CRC is calculated for the first 8 bytes in one clock cycle, but when I try to calculate the CRC over the remaining 6 bytes the results are wrong due to zeros being appended.

Is there a way I can generate the CRC for any length of bytes packet length using a 64-bit parallel CRC generator?

What I've tried:
I used different parallel CRC generators (8-bit parallel CRC, 16-bit parallel CRC generator and so on). But that consumes a lot of FPGA resources. I want to conserve resources using just 64-bit parallel CRC generators.

2
vhdlethernetcrc32data-link-layer
See comp.lang.vhdl Ethernet CRC-32 on Google Groups. - user1155120
Just to clarify, are you receiving the entire packet, storing it, and then calculating the CRC? Or are you trying (/want) to incrementally calculate the CRC from every 64-bit block received? - gsm
@gsm I am not storing the entire packet. I am trying to calculate the CRC32 over the incoming packet on every clock cycle. - Tushar

2 Answers

1
votes

Start with a constant 64-bit data word that brings the effective CRC register to all zeros. Then prepend the message with zero bytes, instead of appending them, putting those zeros on the end of the 64-bit word that is processed first. (You did not provide the CRC definition, so this depends on whether the CRC is reflected or not. If the CRC is reflected, then put the zero bytes in the least-significant bit positions. If the CRC is not reflected, then put them in the most-significant bit positions.) Then exclusive-or the result with a 32-bit constant.

So for the example, you would first feed a 64-bit constant to the parallel CRC generator, then feed two zero bytes and six bytes of message in the first word, and then eight message bytes in the second word. Then exclusive-or the result with the 32-bit constant.

For the standard PKZIP CRC, the 64-bit constant is 0x00000000ffffffff, the 32-bit constant is 0x2e448638, and the prepended zero bytes go in the bottom of the 64-bit word.

If you are in control of the implementation of the CRC generator, then you can probably modify it to initialize the effective CRC register to all zeros when you reset the generator, avoiding the need to feed the 64-bit constant.

0
votes

I can't speak for certain, but if you can pad zeros at the start of your packet instead of at the end, then you should get the right answer. It does depend on the polynomial and the initializer...

See this answer here Best way to generate CRC8/16 when input is odd number of BITS (not byte)? C or Python