Quartus II get stuck at 10% while doing Analysis and Synthesis (something wrong with my memory ram module verilog implementatioon?)

0
votes

I am doing a system that takes from a txt file, a data composed by 57,600 binary numbers, process it with some arithmetic module then store resulting data on 3 sets of output memory ram composed each of them by 57,600 binary numbers . ModelSim works fine, results are as expected but when compiling in Quartus II, it get stuck at 10% and does not do anything for hours until I stop process. Although, when I reduce the size of the implemented output memory one digit it successfully compile within seconds. Size of the output memory are 3 sets of 57.600 binary numbers of 32 bits.

I am suspecting that I am not implementing the memory correct, or something is wrong with the memory usage as I'm doing it, but I am not sure, please any advice? I am looking for the most simple straightforward method to implement this.

This is the module for the ram 

module RAM_OUT (clk, pix_val, w_mem_out, set_ram);

input clk;

input [2:0] w_mem_out;
input [31:0] pix_val;
input set_ram;



reg [15:0] addr_out; // tamano de 57600 datos 


reg [31:0] mem_out1 [0:57599];
reg [31:0] mem_out2 [0:57599];
reg [31:0] mem_out3 [0:57599];

/////////// ram out ///////////////

always @ (posedge clk)

begin
if (set_ram)
addr_out = 0;

else 
    begin

        if (w_mem_out == 1)

                begin
                mem_out1 [addr_out] = pix_val;  
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 2)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out2 [addr_out] = pix_val;  
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 3)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000; 
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = pix_val;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else    

                addr_out = addr_out;


    end

end

//////////////////////////////////

/*


module RAM_OUT (pix_val, w_mem_out, set_ram);


input [2:0] w_mem_out;
input [31:0] pix_val;
input set_ram;



reg [15:0] addr_out; // tamano de 57600 datos 


reg [31:0] mem_out1 [0:57599];
reg [31:0] mem_out2 [0:57599];
reg [31:0] mem_out3 [0:57599];

/////////// ram out ///////////////

always @ (w_mem_out or set_ram)
begin

if (set_ram)
addr_out = 0;

else 
    begin

        if (w_mem_out == 1)

                begin
                mem_out1 [addr_out] = pix_val;  
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 2)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out2 [addr_out] = pix_val;  
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 3)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000; 
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = pix_val;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 4)

                begin
                mem_out1 [addr_out] = pix_val;  
                mem_out2 [addr_out] = pix_val; 
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end


        else if (w_mem_out == 5)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000; 
                mem_out2 [addr_out] = pix_val;
                mem_out3 [addr_out] = pix_val; 

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 6)        

                begin
                mem_out1 [addr_out] = pix_val;  
                mem_out2 [addr_out] = pix_val; 
                mem_out3 [addr_out] = pix_val; 

                addr_out = addr_out + 16'b0000000000000001;
                end


        else    

                addr_out = addr_out;


    end

end

//////////////////////////////////

*/

endmodule
1
memoryverilogfpgasynthesis
My guess is you ran out of available flops for your target FPGA. Your Quartus documentation should have macro module for RAM. Synthesis directives/attributes is another option (simulations treat these as comments). On another note, RAM_OUT doesn't have an output so I'm surprised Quartus did optimize it to nothing – Greg
Thanks so much, I have replaced the code like " reg [31:0] mem_out1 [0:57599]; " and using the memory library megawizard directly connecting the ports in the top modules and it seems its compiling now good. The reason why I left this module without output ports is because i'm still trying to realize how to make the content of the memory somehow readable ( I need to check if the result of the processing is correct). Do you have any suggestions? – sujeto1

1 Answers

3
votes

I can see the following issues with your code:

  1. Data is only being written into mem_out1, mem_out2 and mem_out3. Technically if you are not using the data thats being written into the memory at all, Quartus could just optimize it out and not synthesizae that part at all.

  2. The coding style is not quite right. You could try replacing the '=' (blocking statements) within the always block with '<=' (non blocking).

  3. You can refer the Quartus Prime Handbook (Section 11.4.1) for details on how to write HDL for inferring a RAM. Note that the link is for Quartus Pro 16.0 and some points maybe not be applicable for your version of Quartus software. Refer to the manual corresponding to your Quartus version for correct details.