I want to send a 128-bit value to an FPGA, bit-by-bit, from an AVR. The FPGA expects the following transaction to occur:
1) RST signal to clear the FPGA's 128-bit register. Goes high, then goes low. A "CLOCK" signal is set to low.
2) An ENABLE bit is set to high to indicate that a transfer is underway.
3) An INPUT bit is set to the value of arrayOfBinaryValues[i].
4a) CLOCK signal goes high. On leading edge, the value of INPUT is stored in position i on the FPGA.
4b) CLOCK signal goes low.
4c) INPUT bit set to next value of arrayOfBinaryValues[i]
[Repeat 4a-4c until whole array is sent]
So, I wrote a function to get this done. It happens in stages. Step 1, the user inputs a 32-character value that is stored as a c-string. Since these are characters, I have to convert them to corresponding hex values:
void transmitToFPGA(unsigned char hash[32]) {
// convert the characters to their corresponding hex values
unsigned char hash_hex[32];
unsigned char j = 0;
SET_BIT(FPGA_DDR,MD5_RST); // sets reset bit high
for (unsigned char i=0; i<32; i++) {
switch (hash[i]) {
case '0': hash_hex[i] = 0x00; break;
case '1': hash_hex[i] = 0x01; break;
case '2': hash_hex[i] = 0x02; break;
case '3': hash_hex[i] = 0x03; break;
case '4': hash_hex[i] = 0x04; break;
case '5': hash_hex[i] = 0x05; break;
case '6': hash_hex[i] = 0x06; break;
case '7': hash_hex[i] = 0x07; break;
case '8': hash_hex[i] = 0x08; break;
case '9': hash_hex[i] = 0x09; break;
case 'A': hash_hex[i] = 0x0a; break;
case 'B': hash_hex[i] = 0x0b; break;
case 'C': hash_hex[i] = 0x0c; break;
case 'D': hash_hex[i] = 0x0d; break;
case 'E': hash_hex[i] = 0x0e; break;
case 'F': hash_hex[i] = 0x0f; break;
default: hash_hex[i] = 0x00; break;
}
}
Then I tried converting the corresponding bits into an array of binary values like so:
unsigned char hash_bin[128];
for (unsigned char i=0; i<32; i++) {
hash_bin[j] = hash_hex[i] & 0x01; j++;
hash_bin[j] = hash_hex[i] & 0x02; j++;
hash_bin[j] = hash_hex[i] & 0x04; j++;
hash_bin[j] = hash_hex[i] & 0x08; j++;
}
Then I perform the transmission
// conduct transmission
CLR_BIT(FPGA_DDR,MD5_RST); // clear reset
delay_ms(1);
CLR_BIT(FPGA_DDR,AVR_CLK); // AVR_CLK = 0
delay_ms(1);
CLR_BIT(FPGA_DDR,AVR_EN); // AVR_EN = 0
delay_ms(1);
CLR_BIT(FPGA_DDR,AVR_IN); // AVR_IN = 0
delay_ms(1);
for (unsigned char i=0; i<128; i++) {
CLR_BIT(FPGA_DDR,AVR_CLK); // AVR_CLK = 0
delay_ms(1);
SET_BIT(FPGA_DDR,AVR_EN); // AVR_EN = 1
delay_ms(1);
if (hash_bin[i] == 0) { // AVR_IN = hash_bin[i]
CLR_BIT(FPGA_DDR,AVR_IN);
} else {
SET_BIT(FPGA_DDR,AVR_IN);
}
delay_ms(1);
t SET_BIT(FPGA_DDR,AVR_EN); // AVR_CLK = 1
delay_ms(1);
}
}
Unfortunately, this doesn't seem to work and I'm not entirely sure why. I suspect the way I perform conversion is not working properly. Does anyone have any insights?
edit: This is the VHDL module this code communicates with:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_Slave is
Port ( AVR_IN : in STD_LOGIC;
AVR_CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY : out STD_LOGIC;
HASH_OUT : out STD_LOGIC_VECTOR (127 downto 0) := x"00000000000000000000000000000000" );
end SPI_Slave;
architecture Behavioral of SPI_Slave is
shared variable count : integer := 0;
signal hash : std_logic_vector(127 downto 0);
begin
PROCESS(AVR_CLK, ENABLE)
BEGIN
IF (ENABLE = '1') THEN -- If ENABLE is HIGH
IF (rising_edge(AVR_CLK)) THEN -- If CLK goes HIGH
IF (RST = '1') THEN -- If RST is HIGH
hash <= x"00000000000000000000000000000000"; -- then zero HASH_OUT and count
count := 0;
READY <= '0';
ELSE -- Otherwise, if RST is LOW
IF (count > 126) THEN
hash(count) <= AVR_IN;
HASH_OUT <= hash (127 downto 0);
READY <= '1';
count := count + 1;
ELSE
hash(count) <= AVR_IN;
count := count + 1;
READY <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
end Behavioral;
